CANCELLATION CIRCUITS AND TRANSCEIVER CIRCUITS TO SUPPRESS INTERFERENCE

摘要

An interference-cancelling circuit includes a main delay line, a first power divider, a first power combiner, and first circuits. The main delay line delays a number of transmitting signals. The first power divider is coupled to the main delay line. Each of the first circuits including n branch circuits is configured to generate cancellation signals for canceling leakage signals (where “n” is an integer of 2 or more). A first branch circuit of the n branch circuits is coupled between the first power divider and the first power combiner. A (k−1)-th branch circuit of the n branch circuits is coupled to a k-th branch circuit of the n branch circuits (where “k” is an integer from 2 to n). The first power combiner outputs cancellation signals generated by the first circuit. A transceiver circuit is also provided.

主权项

1. A cancellation circuit, comprising:
a main delay line delaying a number of transmitting signals of a transmitter; a first power divider having an input terminal coupled to the main delay line; a first power combiner; and a plurality of first circuits generating a plurality of the first cancellation signals for canceling a plurality of leakage signals according to the delayed transmitting signals, wherein: the first circuit comprises n branch circuits, a first branch circuit of the n branch circuits is coupled between the first power divider and the first power combiner, a (k−1)-th branch circuit of the n branch circuits is coupled to a k-th branch circuit of the n branch circuits, where the parameter “k” is from 2 to n, and the parameters “k” and “n” are integer numbers, and the first power combiner outputs the first cancellation signals generated by the first circuits.