发明名称 |
COMPUTER BASED SYSTEM FOR VERIFYING LAYOUT OF SEMICONDUCTOR DEVICE AND LAYOUT VERIFY METHOD THEREOF |
摘要 |
There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout. |
申请公布号 |
US2016085903(A1) |
申请公布日期 |
2016.03.24 |
申请号 |
US201514843491 |
申请日期 |
2015.09.02 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
HAN Changho |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method of verifying a Fin-based integrated circuit layout using a layout verifying system, the method comprising:
receiving a layout corresponding to a specific integrated circuit unit; extracting one or more device codes from the layout, each device code being based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins; and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. |
地址 |
Suwon-si KR |