发明名称 |
MODEL ORDER REDUCTION IN TRANSISTOR LEVEL TIMING |
摘要 |
A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling. |
申请公布号 |
US2016085890(A1) |
申请公布日期 |
2016.03.24 |
申请号 |
US201414495383 |
申请日期 |
2014.09.24 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALLEN Robert J.;DANAN Yanai;RAO Vasant;SOREFF Jeffrey P.;ZHAO Xin |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method comprising reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing comprises:
compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling. |
地址 |
Armonk NY US |