发明名称 TOLERANT INPUT CIRCUIT AND TOLERANT CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide a tolerant input circuit and a tolerant control method capable of suppressing functional degradation due to lower power supply voltage.SOLUTION: A tolerant input circuit 10 includes: a parallel circuit 16 configured with a parallel connection of an N-type transistor 22 inputted with VDD as a gate voltage, and a P-type transistor 24; a first inverter circuit 30 for outputting either a GND voltage or a VDD voltage as a comparison result of an output voltage of the parallel circuit 16 and a theoretical threshold value; and a control part 20 for controlling the gate voltage of the P-type transistor 24 according to an outputted GND voltage or VDD voltage outputted as a comparison result by the first inverter circuit.SELECTED DRAWING: Figure 1
申请公布号 JP2016040868(A) 申请公布日期 2016.03.24
申请号 JP20140164307 申请日期 2014.08.12
申请人 LAPIS SEMICONDUCTOR CO LTD 发明人 NAGAYAMA ATSUSHI
分类号 H03K19/0175 主分类号 H03K19/0175
代理机构 代理人
主权项
地址