| 摘要 |
<p>813,768. Comparing digital data. STANDARD TELEPHONES & CABLES Ltd. Jan. 25, 1957 [Jan. 31, 1956], No. 2780/57. Class 106 (1). In an electrical circuit for comparing sequentially pairs of corresponding digits of two ndigit binary numbers, a shift register having at least n +1 stages stores one number and receives the digits of the other number, the contents of the register being shifted one stage for each digit received, and comparison means is controlled by a predetermined pair of register stages, the result of the comparison indicating whether the two numbers are equal or which is the greater. The shift register SR shown may be as described in Specifications 663,574, 726,526 and 783,000, [all in Group XL (b)], the outputs of the first and last stages 1 and n+ 1 being applied to gates G3, G4 and, through inverters, to gates G6, G5 in comparator CMP. The numbers are represented by serial pulse trains (pulse for "0," no pulse for " 1," and most significant digit first) applied to P2 in synchronism but out of phase with clock pulses applied to P1 as shown, the pulses being obtained, e.g. from a magnetic tape reading circuit as described in Specification 766,317, [Group XL (b)]. In response to each pulse P1, monostable device produces a shift-registeradvancing pulse at P11 of duration K1T (T being the inter-pulse period). After the 1st number has been registered in stages 1 to n, a potential applied to PA sets bi-stable device BS1 to condition " 1 " thus opening gate G2. As the 2nd number is applied to P2, each clock pulse at P1 is therefore applied to MS2, as well as MS1, to produce at P12 a comparisoneffecting pulse delayed by K2T (lying between (T/2 and T). Since the shift register stages provide an effective output for " 0," if an " 0 " in the 2nd number (from stage 1) corresponds to a " 1 " in the 1st number (from state n+1), the delayed pulse passes through gates G3, G5 and sets bi-stable device BS2 to " 0." Similarly, if a " 1 " in the 2nd number corresponds to an " 0 " in the 1st number, BS2 is set to " 1." Any pulse which sets BS2 will also pass through buffer G1 to reset BS1 and prevent any further delayed pulses being obtained. Thus the condition of BS2 indicates which number is greater, equality being indicated by BS1 finally remaining in the " 1 " condition. Reference is made to reading and comparing information recorded magnetically on a tape or drum, or on a cheque or on a piece of tape associated with a chequeholding jacket. To permit wider tolerances in the relative phase of clock and information pulses, the shift register may have an additional stage " 0 " (Fig. 2, not shown), and the pulses at P1 lag behind the pulses at P2. The period K2T can then lie between K1T and T. Specifications 730,854 and 766,318 also are referred to.</p> |
