| 摘要 |
PROBLEM TO BE SOLVED: To accurately synchronize an original clock signal and a clock signal at a destination of reception even if a circuit length of distribution route of a clock signal is too long to ignore in comparison with a wavelength of the signal.SOLUTION: A clock signal distribution circuit is connected to a reception circuit to which a second clock signal that is obtained by delaying a first clock signal just for a first delay time is propagated, for receiving a third clock signal by a first route that does not include a branch including a second delay time and is connected to a starting end and a terminal of a second route that does not include a branch including a delay time that is twice as long as the second delay time. The clock signal distribution circuit includes: means for detecting a third delay time during which a first reference signal transmitted to the starting end is propagated, of a second reference signal received from the terminal relative to the first reference signal; and means for calculating a fourth delay time by subtracting a time that is a half of the third delay time, from a cycle of the first clock signal, and transmitting the second clock signal that is obtained by delaying the first clock signal just for the fourth delay time, to the first route.SELECTED DRAWING: Figure 1 |
