Method and apparatus for performing timing closure analysis when performing register retiming

摘要

A method for designing a system on a target device includes performing register retiming on the system. A critical chain in the system is detected, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths. The system is modified in response to properties of the critical chain.

主权项

1. A method for designing a system on a target device, comprising:
performing register retiming on the system; detecting a critical chain in the system in response to the register retiming, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths; and modifying the system in response to properties of the critical chain, wherein the modifying includes removing register retiming constraints that prohibit movement of a register for register retiming, and wherein at least one of the performing, detecting, and modifying is performed by a processor.