Low-pin-count non-volatile memory interface for 3D IC

摘要

A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one die can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each die in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.

主权项

1. An integrated circuit, comprising:
a plurality of integrated circuit dies arranged in a stack, at least one of the integrated circuit dies having at least one low-pin-count (LPC) One-Time-Programmable (OTP) memory; and interface pins of the at least one low-pin-count OTP memory in the at least one of the integrated circuit dies being coupled to a set of low-pin-count pins that are externally accessible to the at least one the integrated circuit dies, wherein the at least one of the integrated circuit dies in the integrated circuit are configured to be selectable and configured to be readable or programmable using the set of the low-pin-count pins.