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1. A NAND memory array with a 2-level metal broken-BL hierarchical architecture for performing continuous and concurrent multiple-WL Program, Read, Erase, Erase-Verify, and Program-Verify operations in dispersed Blocks in a same or multiple different NAND planes, the NAND memory array comprising:
a plane of NAND array cells made of a plurality of Blocks having 2N columns in Y direction and a plurality of rows in X direction, the plane being built on a common Triple-Pwell (TPW) region over a deep-Nwell region on a P-substrate, the X direction being perpendicular to the Y direction, the plane including J Groups in the Y direction, each Group including L Segments in the Y direction, each Segment including m sub-Segments in the Y direction, each sub-Segments including K Blocks in the Y direction, each Block including M rows or 2N strings of NAND array cells in the X direction capped respectively by a first row of 2N string-select devices and a second row of 2N string-select devices, each of M rows of NAND array cells forming a page having a common gate connected to a word line (WL), the first/second row of 2N string-select devices having a common gate line coupled to a first/second gate signal, a source node of the second row of 2N string-select devices being connected to a common source line, N being a multiplier of a byte, J, L, m, and K being properly selected integer numbers including 4, 8, 16, 32, 64, 128; N global bit lines (GBLs) laid in parallel extended the full plane in the Y direction as top-level metal lines with a first pitch; J−1 rows of N GBL-divided devices disposed in the X direction with a common gate line coupled to a third gate signal and configured to respectively divide each GBL to J broken-GBLs, each broken-GBL being associated with one column of NAND array cells in one Group connecting all L Segments therein; 2N local bit lines (LBLs) laid in parallel extended to all strings in one Segment in the Y direction as bottom-level metal lines with a second pitch below the top-level metal lines; a first row of N first Segment-select devices disposed for each Segment of each Group and configured to respectively connect each broken-GBL in a Group to an odd number LBL associated with a selected Segment of the Group, the first row of N first Segment-select devices having a common gate line coupled to a fourth gate signal; a second row of N second Segment-select devices disposed next to each first row of N first Segment-select devices and configured to respectively connect each said broken-GBL in the Group interleavingly to a next even number LBL associated with the selected Segment of the Group, the second row of N second Segment-select devices having a common gate line coupled to a fifth gate signal; m−1 rows of 2N LBL-divided devices disposed in the X direction with a common gate line coupled to a sixth gate signal and configured to respectively divide each LBL to m broken-LBLs, each broken-LBL being associated with one column of NAND array cells in one sub-Segment connecting all K Blocks therein and configured to connect respectively to a drain node of the first string-select device of one string of NAND array cells in each of K Blocks of said sub-Segment; and a row of 2N LBL-precharge devices disposed in the X direction with a common gate line coupled to a seventh gate signal and configured to respectively connect each broken-LBL to a common dedicated metal power line for each sub-Segment of each Segment of each Group; wherein the first, second, third, fourth, fifth, sixth, and seventh gate signals and all WL voltages controlled by corresponding decoders with latch designs and one common dedicated metal power line associated with 2N broken-LBLs per sub-Segment or 2N LBLs per Segment are configured for performing multi-task concurrent/pipeline operations of multiple-WL or partial-WL Program in dispersed Blocks flexibly based on any sub-Segment and of multiple-WL or partial-WL Read, Erase-Verify, and Program-Verify in dispersed Blocks flexibly based on any Segment in a same plane or multiple different planes with multiple-fold performance improvements. |
