Scan warmup scheme for mitigating di/dt during scan test

摘要

We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

主权项

1. A method, comprising:
loading a scan test stimulus to a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; unloading a scan test response from the first set of logic elements at the scan clock first frequency; adjusting the scan clock from the scan clock first frequency to a scan clock second frequency by ramping up the scan clock from the first frequency to the second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency, and wherein the test clock frequency is less than the system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency; and wherein the adjusting mitigates a drop in voltage of a power supply to the integrated circuit associated with a transition of the scan clock from the first frequency to the second frequency, by reducing a change in current draw within a predetermined time period.