| 摘要 |
The present invention relates to a multi-delay line clock generator on a delayed-locked loop. The multi-delay line clock generator comprises: a first voltage control delay line consisting of n delay units serially connected with n edge detectors; and a second voltage control delay line consisting of n delay units serially connected with n edge detectors. A signal outputted from a device constituting a protonic delay unit is utilized as input of an edge detector. When the multi-delay line clock generator on a delayed-locked loop according to the present invention is used, a procedure may be maintained at low costs, and a clock of a higher frequency may be generated. |
