Power MOSFET current sense structure and method

摘要

A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

主权项

1. A power metal-oxide-semiconductor-field-effect-transistor (MOSFET), comprising:
a substrate having upper and lower surfaces; a main field effect transistor (MFET) formed in the substrate, having multiple MFET source regions and MFET gate runners extending to the upper surface, underlying an MFET source metal coupled to the multiple MFET source regions, and a drain region and a drain contact proximate the lower surface; a current sensing field effect transistor (SFET) formed in the substrate, having multiple SFET source regions and SFET gate runners extending to the upper surface, underlying an SFET source metal coupled to the multiple SFET source regions, and a drain region and a drain contact proximate to the lower surface, wherein the SFET is laterally embedded within the MFET but separated from the MFET by a buffer region; and isolation gate runners located in the buffer region and electrically coupling the MFET gate runners to the SFET gate runners while electrically separating the MFET source regions and the SFET source regions, wherein the isolation gate runners are connected end-to-end such that each of the isolation gate runners has at least one end directly physically connected to an end of an adjacent isolation gate runner, and adjacent isolation gate runners have one common end directly physically coupled to one of the MFET gate runners, and each of the isolation gate runners has a middle portion directly physically connected to one of the SFET gate runners.