Memory and memory controller for high reliability operation and method

摘要

In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.

主权项

1. A system comprising:
a memory system; and a data processor having an output for coupling to said memory system, for providing selected ones of a normal command and an adjacent command based on a number of activate commands sent to a row in said memory system during a predetermined time window, wherein said data processor determines timing eligibility of a subsequent normal command based on a parameter specifying a time from said adjacent command to said subsequent normal command, wherein said memory system is responsive to said adjacent command and a row address to perform an operation on said row address, and to refresh first and second row addresses adjacent to said row address.