ESD transistor and a method to design the ESD transistor

摘要

An IC design that has an ESD transistor is disclosed. The IC includes a transistor, a ballast resistor, a routing structure and a coupling. The transistor includes a gate, a source and a drain. The ballast resistor is extending parallel to the gate of the transistor. The coupling connects the source of the drain of the transistor the ballast resistor. The routing structure connects the ballast resistor to the remaining of the circuitry. A method to design the IC is also disclosed. The ESD transistor provides means of protection against the ESD surges.

主权项

1. An electro static discharge (ESD) protection device comprising:
a transistor that includes a gate of the transistor, a first diffusion area as a source of the transistor and a second diffusion area as a drain of the transistor, wherein the first diffusion area is adjacent to the second diffusion area, the gate covers a region between the first diffusion area and the second diffusion area, and the transistor provides protection from electrostatic discharge; a first dummy gate that is adjacent to the first diffusion area and is substantially parallel with the gate of the transistor, the first dummy gate having a first single, unitary body, wherein the first dummy gate provides further protection from electrostatic discharge; a routing structure located in a layer different than the gate of the transistor, the routing structure coupled to the first dummy gate; a first coupling that couples the first diffusion area to the first dummy gate; a second coupling that couples the first diffusion area to the first dummy gate, the second coupling in electrical parallel with the first coupling; a second dummy gate that is adjacent to the second diffusion area and is substantially parallel with the gate of the transistor, the second dummy gate having a second single, unitary body, wherein the second dummy gate provides further protection from electrostatic discharge; and a third coupling that couples the second diffusion area to the second dummy gate.