Voltage droop reduction by delayed back-propagation of pipeline ready signal

摘要

A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

主权项

1. A method for generating flow-control signals, comprising:
generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal that is received from a second pipeline stage and a throttle disable signal; generating, by the first pipeline stage, a downstream valid signal based on an upstream valid signal and the delayed ready signal; and, generating, by the first pipeline stage, an upstream ready signal based on the delayed ready signal and the downstream valid signal; wherein generating the delayed ready signal comprises: generating an internal ready signal by performing a logic OR operation between the downstream ready signal and a logical inverse of the downstream valid signal, generating a delayed internal ready signal based on the internal ready signal and a time delay, and performing a logical OR operation between the delayed internal ready signal and the throttle disable signal to generate the delayed ready signal.