发明名称 |
Intelligent multicore control for optimal performance per watt |
摘要 |
The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget. |
申请公布号 |
US9292293(B2) |
申请公布日期 |
2016.03.22 |
申请号 |
US201314074908 |
申请日期 |
2013.11.08 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Park Hee-Jun;Thomson Steven S;Alton Ronald Frank;Regini Edoardo;Goverdhan Satish;Backer Pieter-Louis Dam |
分类号 |
G06F1/32;G06F9/38;G06F1/20;G06F9/50 |
主分类号 |
G06F1/32 |
代理机构 |
The Marbury Law Group, PLLC |
代理人 |
The Marbury Law Group, PLLC |
主权项 |
1. A method for multicore control of a plurality of processor cores of a multicore integrated circuit, comprising:
comparing temperature readings of the plurality of processor cores to a temperature threshold; calculating a map for the plurality of processor cores based on processor core information and a plurality of hypothetical cases, wherein a first map is calculated in response to the temperature readings of the plurality of processor cores being less than the temperature threshold and a second map is calculated in response to the temperature readings of the plurality of processor cores being greater than the temperature threshold; identifying, from the first map, a first configuration of processor cores to optimize power consumption for a given workload; identifying, from the second map, a second configuration of processor cores to optimize performance for a given power budget; and controlling an activity state for each processor core of the plurality of processor cores based on the identified configuration. |
地址 |
San Diego CA US |