发明名称 In-phase and quadrature radio frequency digital-to-analog converter
摘要 Disclosed herein is an apparatus for radio frequency digital-to-analog conversion of in-phase and quadrature bit streams. The apparatus may include a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells. Each multiplying cell produces an output signal based on a received input bit. The output signals from each multiplying cell combine in phase on the connected output line.
申请公布号 US9294328(B2) 申请公布日期 2016.03.22
申请号 US201514878856 申请日期 2015.10.08
申请人 The Boeing Company 发明人 Baringer Cynthia D.;Hitko Donald A.
分类号 H04L27/36;H04L27/26 主分类号 H04L27/36
代理机构 Kunzler Law Group, PC 代理人 Kunzler Law Group, PC
主权项 1. An apparatus, comprising: a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, each in-phase multiplying cell producing an output signal based on a received one of the plurality of in-phase bits, wherein each in-phase bit has a significance from most significant to least significant and a binary-weighted number of in-phase multiplying cells are connected to each in-phase bit, the binary-weighted number matching the significance of the in-phase bit; a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, each quadrature multiplying cell producing an output signal based on the received one of the plurality of quadrature bits, wherein each quadrature bit has a significance from most significant to least significant and a binary-weighted number of quadrature multiplying cells are connected to each quadrature bit, the binary-weighted number matching the significance of the quadrature bit; a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, the first output line propagating a first output signal produced from output signals of the first set of the plurality of in-phase multiplying cells and the first set of the plurality of quadrature multiplying cells; and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells, the second output line propagating a second output signal produced from output signals of the second set of the plurality of in-phase multiplying cells and the second set of the plurality of quadrature multiplying cells.
地址 Chicago IL US