发明名称 Memory circuit and memory device
摘要 To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.
申请公布号 US9293193(B2) 申请公布日期 2016.03.22
申请号 US201514679110 申请日期 2015.04.06
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Ohmaru Takuro
分类号 G11C11/00;G11C11/419;G11C7/12;G11C11/412 主分类号 G11C11/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A memory circuit comprising: a latch unit; a first switch unit between a first signal line and the latch unit; a second switch unit between a second signal line and the latch unit; and a third switch unit between the latch unit and a power supply line, wherein the latch unit comprises a first inverter and a second inverter, an input terminal of the first inverter is electrically connected to an output terminal of the second inverter, and an input terminal of the second inverter is electrically connected to an output terminal of the first inverter, wherein the first inverter comprises a field-effect transistor, and wherein each of a gate of the field-effect transistor, the first switch unit, the second switch unit, and the third switch unit is supplied with a control signal.
地址 Kanagawa-ken JP