Memory controller and information processing apparatus

摘要

A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

主权项

1. A memory controller comprising:
a first terminal connected to a Dual Inline Memory Module (DIMM) and configured to output an address signal to the DIMM; a second terminal connected to the DIMM; a first transmission line connected to the second terminal and configured to transmit first data to be written to the DIMM; a second transmission line connected to the second terminal and configured to transmit second data read from the DIMM; a determination part configured to determine a type of the DIMM having a specific address line topology, the determination being made based on Serial Presence Detection (SPD) of the DIMM; a slew rate setting part configured to set a slew rate of the address signal based on the type of the DIMM determined by the determination part, the slew rate setting part setting a first slew rate of the address signal input to a Registered Dual Inline Memory Module (RDIMM) lower than a second slew rate of the address signal input to an Unbuffered Dual Inline Memory Module (UDIMM) in a case where the type of the DIMM determined by the determination part is an RDIMM, the slew rate setting part setting the second slew rate of the address signal in a case where the type of the DIMM determined by the determination part is a UDIMM; a delay command generating part configured to generate a delay command for setting a delay time based on the type of the DIMM determined by the determination part; a first delay control part inserted in series into the first transmission line and configured to control the delay time in response to the delay command generated by the delay command generating part and to delay the first data by the delay time when writing the first data in a case where the type of the DIMM determined by the determination part is an RDIMM; and a second delay control part inserted in series into the second transmission line and configured to control the delay time in response to the delay command generated by the delay command generating part and to delay the second data by the delay time when reading the second data in a case where the type of the DIMM determined by the determination part is a UDIMM.