Semiconductor memory apparatus and semiconductor integrated circuit apparatus

摘要

A memory control circuit 10 controls an operation of reading stored data from a memory cell 50 connected to a word line WL and a bit line BL based on an address Address including a row address Ax and a column address Ay. When the address Address includes redundancy addresses P1 to P4 designating a word line WLa or a bit line BLc connected to a specific memory cell Cc, redundancy decoders 13-1 to 13-4 replace the specific memory cell Cc with a redundancy memory cell RCc connected to redundancy word lines RWL1 and RWL2 or redundancy bit lines RBL1 and RBL2. Redundancy address latch circuits 12-1 to 12-4 respectively hold the redundancy addresses P1 to P4, and erase the held redundancy addresses P1 to P4 based on a reset signal RS inputted from the memory control circuit 10.

主权项

1. A semiconductor memory apparatus, comprising:
a plurality of memory cells, respectively connected to a plurality of word lines and bit lines intersecting each other, and storing data inputted from the bit lines; a memory control circuit, based on an address comprising a row address designating each of the word lines and a column address designating each of the bit lines, controlling an operation of reading the stored data from the memory cell connected to the word line and the bit line designated by the row address and the column address; a redundancy decoder, when the address comprises a redundancy address designating a word line or bit line connected to a specific memory cell, replacing the specific memory cell with a redundancy memory cell connected to a predetermined word line or bit line in the plurality of memory cells; and a plurality of redundancy address latch circuits, respectively holding the redundancy addresses, and erasing the held redundancy addresses based on a reset signal inputted from the memory control circuit.