发明名称 Methods and structures for back end of line integration
摘要 Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
申请公布号 US9293363(B2) 申请公布日期 2016.03.22
申请号 US201514805443 申请日期 2015.07.21
申请人 GLOBALFOUNDRIES INC. 发明人 Singh Sunil K.;Srivastava Ravi P.;Zaleski Mark A.;Sehgal Akshey
分类号 H01L29/66;H01L21/4763;H01L21/311;H01L21/768;H01L23/532;H01L23/528;H01L23/522;H01L21/02;H01L21/3105;H01L21/3213 主分类号 H01L29/66
代理机构 Williams Morgan, P.C. 代理人 Williams Morgan, P.C.
主权项 1. A method of forming a semiconductor structure, comprising: depositing a first dielectric layer on a semiconductor substrate; depositing a first layer of direct self-assembly (DSA) material on the first dielectric layer; performing a phase separation of the first layer of DSA material into a first phase region and a second phase region; selectively etching one phase region of the first phase region and second phase region of the first layer of DSA material; forming cavities in the first dielectric layer; depositing a metal fill layer in the cavities of the first dielectric layer; depositing a second layer of DSA material over the metal fill layer; performing a phase separation of the second layer of DSA material into a first phase region and a second phase region; selectively etching one phase region of the first phase region and second phase region of the second layer of DSA material; forming cavities in the metal fill layer; and depositing a second dielectric layer over the metal fill layer and in the metal layer cavities.
地址 Grand Cayman KY