METHOD AND SYSTEM OF GENERATING LAYOUT

摘要

Disclosed is a method of generating a layout usable for fabricating an integrated circuit. The method includes a step of generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. A step of generating the second conductive layout layer includes a step of performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.