| 摘要 |
The invention discloses a clock phase judgment circuit and judgment method in a clock data recovery circuit of a high-speed serial interface receiving terminal in the technical field of circuit design and data transmission. The judgment circuit comprises a first phase discriminator, a second phase discriminator, a third phase discriminator, a fourth phase discriminator, a first vote unit, a second vote unit and a third vote unit. According to the invention, firstly demux on two high-speed signals is performed to obtain fours relatively low-speed signals to be input to the clock phase judgment circuit; secondly the phase discriminators in the clock phase judgment circuit are used for processing the fours signals respectively to obtain early/late information by judging; and finally the vote units in the clock phase judgment circuit are used for voting the four groups of early/late information to obtain synthetic early/late information. The clock phase judgment circuit outputting the early information, the late information and a hold signal respectively represents a sampling clock needing to be moved forward, to be moved backward, and to be unchanged. The clock phase judgment circuit provided by the invention can enable not only the bandwidth in a clock data recovery loop circuit to be reduced by half, but also the speed of a digital module to be lowered by half, and has simple design, low power consumption and small occupied area. |
