发明名称 SEMICONDUCTOR DEVICE
摘要 According to one embodiment, there is provided a semiconductor device including an interposer, a logic chip, a memory chip, and a package substrate. In the interposer, first via is configured to electrically connect a signal terminal of the logic chip and a signal terminal of the memory chip to each other through a substrate. Multi-layer wiring is disposed on first principal surface side of the substrate. Power supply terminal of the logic chip is electrically connected to the multi-layer wiring. Power supply pad is disposed on the first principal surface side of the substrate and configured to be electrically connected to the power supply terminal of the logic chip through the multi-layer wiring. A metal wire is connected to power supply pad. The package substrate includes a power supply wiring. The power supply pad and the power supply wiring are electrically connected to each other through the metal wire.
申请公布号 US2016079219(A1) 申请公布日期 2016.03.17
申请号 US201514645333 申请日期 2015.03.11
申请人 Kabushiki Kaisha Toshiba 发明人 Hosomi Eiichi
分类号 H01L25/18;H01L23/31;H01L23/498 主分类号 H01L25/18
代理机构 代理人
主权项 1. A semiconductor device comprising: an interposer; a logic chip mounted on a first principal surface of the interposer; a memory chip mounted on a second principal surface of the interposer, the second principal surface is a principal surface arranged on an opposite side of the first principal surface; and a package substrate on which the logic chip, the interposer, and the memory chip are mounted, the interposer including: a substrate; a first via configured to electrically connect a signal terminal of the logic chip and a signal terminal of the memory chip to each other through the substrate; a multi-layer wiring disposed on the first principal surface side of the substrate, a power supply terminal of the logic chip being electrically connected to the multi-layer wiring; and a power supply pad disposed on the first principal surface side of the substrate and configured to be electrically connected to the power supply terminal of the logic chip through the multi-layer wiring, a metal wire being connected to the power supply pad, the package substrate including a power supply wiring, and the power supply pad and the power supply wiring being electrically connected to each other through the metal wire.
地址 Tokyo JP