PROGRAMMABLE DELAY CIRCUIT BLOCK

摘要

A programmable delay circuit block (100) includes an input stage (102) having a cascade input (112) and a clock input (114), wherein the input stage (102) passes a signal received at the cascade input (112) or a signal received at the clock input (114). The programmable delay circuit block (100) further may include a delay block (104) configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage (102) and a pulse generator (106) configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block 100 also includes an output stage (108) having a cascade output (148) and a clock output (152). The output stage (108) is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output (148) and pass the signal received at the clock input (114), the inverted version of the pulse signal, or the delayed signal from the clock output (152).