3D TAP & SCAN PORT ARCHITECTURES

摘要

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

主权项

1. An integrated circuit die comprising:
(a) a bottom surface including bottom parallel test input signal contact points, bottom parallel test output signal contact points, a test clock in signal contact point, a test mode select in signal contact point, a test reset in signal contact point, a bottom test data in signal contact point, and a bottom test data out signal contact point; (b) a top surface including top parallel test output signal contact points, top parallel test input signal contact points, a test clock out signal contact point, a test mode select out signal contact point, a test reset out signal contact point, a top test data out signal contact point, a top test data in signal contact point, and an UP signal contact point; (c) test circuitry having an input coupled to the test clock in signal contact point, an input coupled to the test mode select in signal contact point, an input coupled to the test reset in signal contact point, and an input coupled to the bottom test data in signal contact point, and having control outputs; (d) capture, shift, update circuitry having a clock input coupled with the a test clock in signal contact point, a test mode select input coupled with the test mode select in signal contact point, a capture shift output, an update output, and a scan clock output; and (e) scan circuitry having an input coupled to the bottom test data in signal contact point, an output coupled to the bottom and top test data out signal contact points, and having a capture shift input coupled with the capture shift output, an update input coupled with the update output, a scan clock input coupled with the scan clock output, and a control input coupled with a control output.