| 发明名称 |
CLOCK GATING CIRCUITS AND CIRCUIT ARRANGEMENTS INCLUDING CLOCK GATING CIRCUITS |
| 摘要 |
Clock gating circuits may include: a first inverter; a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter; a feedback circuit having an input-output terminal, the input-output terminal of the feedback circuit coupled to the second terminal of the first switch; and a first logic gate having a first input terminal and a second input terminal, the first input terminal coupled to the input-output terminal of the feedback circuit, the second input terminal electrically connected to receive a master clock signal. |
| 申请公布号 |
US2016077544(A1) |
申请公布日期 |
2016.03.17 |
| 申请号 |
US201414488588 |
申请日期 |
2014.09.17 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Tzeng Jiann-Tyng;Shen Meng-Hung;Chen Yi-Feng;Young Charles Chew-Yuen |
| 分类号 |
G06F1/08 |
主分类号 |
G06F1/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A clock gating circuit comprising:
a first inverter; a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter; a feedback circuit having an input-output terminal, the input-output terminal of the feedback circuit coupled to the second terminal of the first switch; and a first logic gate having a first input terminal and a second input terminal, the first input terminal coupled to the input-output terminal of the feedback circuit, the second input terminal electrically connected to receive a master clock signal. |
| 地址 |
Hsin-Chu TW |
