Manufacturing Method of Power MOSFET Using a Hard Mask as a CMP Stop Layer Between Sequential CMP Steps

摘要

A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

主权项

1. A manufacturing method of a power MOSFET comprising the steps of:
(a) providing a semiconductor wafer having both an over-substrate epitaxy layer of a first conductivity type on a first main surface side and a substrate layer of the first conductivity type on a second main surface side; (b) forming a hard mask film over the first main surface of the semiconductor wafer; (c) patterning the hard mask film; (d) forming a plurality of trenches over the first main surface of the semiconductor wafer by using the patterned hard mask film as a mask; (e) after the step (d) above, removing a portion of the hard mask film so as to leave, as a CMP stop film, the hard mask film in both: a first hard mask film remaining region inside each of a plurality of chip regions that are arranged over the first main surface in a lattice pattern; and a second hard mask film remaining region of a scribe region adjacent to each of the chip regions; (f) depositing, in a state where the CMP stop film is present in each of the chip regions and the scribe region, an embedded epitaxy layer of a second conductivity type opposite to the first conductivity type, over the first main surface of the semiconductor wafer by embedded epitaxial growth; (g) after the step (f) above, performing a first CMP treatment on the first main surface of the semiconductor wafer by using the CMP stop film as a CMP stopper; (h) after the step (g) above, removing the CMP stop film; and (i) after the step (h) above, performing a second CMP treatment on the first main surface of the semiconductor wafer.