Low Power Debug Architecture For System-On-Chips (SoCs) And Systems

摘要

In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.

主权项

1. An apparatus comprising:
a central debug unit to receive debug signals from a plurality of sources including at least one hardware source, at least one firmware source, and at least one software source; a trace merge unit to receive the debug signals from the central debug unit and having an arbitration logic to select between the debug signals from one or more of the plurality of sources and functional debug signals from a plurality of hardware units, the trace merge unit to time stamp the selected debug signals or functional debug signals; a parallel trace interface to receive the time stamped selected debug signals or functional debug signals and to parallelize the time stamped selected debug signals or functional debug signals; a serial trace interface to receive the time stamped selected debug signals or functional debug signals and to serialize the time stamped selected debug signals or functional debug signals; and a selection unit to receive the debug signals from the central debug unit and the parallelized time stamped selected debug signals or functional debug signals from the parallel trace interface and to select one of the debug signals and the parallelized time stamped selected debug signals or functional debug signals for output on an output path, wherein the output path is to be selected from a plurality of output paths.