| 摘要 |
Circuits and methods for reducing leakage are provided. In one example, a system (100) includes circuitry to reset a particular logic circuit (110a-110e, 120a-120d) to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit (110a-110e, 120a-120d) includes the combinational logic (120a-120d) as well as flip flops (110a-110e) that output a state to the combinational logic. Some of the flip flops are "SET" flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are "RESET" flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage. |
