发明名称 RESISTANCE CHANGE MEMORY, METHOD OF MANUFACTURING RESISTANCE CHANGE MEMORY, AND FET
摘要 According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.
申请公布号 US2016079309(A1) 申请公布日期 2016.03.17
申请号 US201514747215 申请日期 2015.06.23
申请人 Kabushiki Kaisha Toshiba 发明人 OTA Kensuke;Saitoh Masumi
分类号 H01L27/24;H01L45/00 主分类号 H01L27/24
代理机构 代理人
主权项 1. A resistance change memory comprising: a first conductive line; a second conductive line provided above the first conductive line, and extending in a first direction; a third conductive line extending in a second direction intersecting the first direction; a select transistor provided between the first and third conductive lines; and a resistance change layer provided between the second and third conductive lines, wherein the select transistor includes: a first conductive layer provided on the first conductive line; a first semiconductor layer as a channel including crystal grains, the first semiconductor layer being provided on the first conductive layer; a second conductive layer provided on the first semiconductor layer, and connected to the third conductive line; and a fourth conductive line as a gate extending in the first direction, the fourth conductive line facing to the first semiconductor layer and being provided between the first and second conductive lines, wherein the first conductive layer and the first semiconductor layer include a predetermined impurity with a first impurity concentration and the second conductive layer includes no predetermined impurity or the predetermined impurity with a second impurity concentration less than the first impurity concentration.
地址 Minato-ku JP