DEFERRED INTER-PROCESSOR INTERRUPTS

摘要

A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

主权项

1. A data processing system comprising:
a first processor; a second processor; an interrupt controller coupled to the first processor and to the second processor, the interrupt controller having a delayed inter-processor interrupt (IPI) register that is configured, when set by the first processor, to indicate that the first processor has requested a delayed IPI, and the interrupt controller having a timer to determine when a period expires, the period starting in response to the interrupt controller receiving the delayed IPI, and the interrupt controller being configured to wake up the second processor and to assign a runnable thread to the second processor to process the runnable thread when the timer expires, and wherein the interrupt controller is coupled to one or more devices or sources to receive interrupts for processing.