IC PHYSICAL DESIGN USING A TILING ENGINE

摘要

In general, embodiments of the present invention provide systems, methods and computer readable media for generating a tiling for a physical placement of a plurality of circuits. The method includes generating a tiling including a plurality of tiles, where each tile identifies a tile geometric area, and a list of one or more of the circuits to be placed in the tile geometric area. The tiling is based on a description of one or more user constraints, where each user constraint identifies a constraint geometric area, and a characteristic of circuits to be placed in the constraint geometric area.

主权项

1. A computer system comprising a tiling engine configured to transform a circuit netlist and a set of user constraints to a physical layout representative of the circuit, the tiling engine comprising:
a constraint translator configured to generate a list of constraint objects in accordance with the set of user constraints and a set of rules stored in a database, each constraint object defining a physical region and a list of circuit cells to be included in the physical region; and a tile generator configured to generate a constraint tree comprising a plurality of levels each associated with a different one of the constraint objects and defining at least one region in which a circuit cell is to be placed.