| 摘要 |
A processor has a debug state, in which it executes instructions received from the debug interface. It has a control parameter, which prevents the execution of instructions at a predefined privilege level, when in the debug state. If, when in the debug state with the parameter set, an exception is signalled, which is executed in the predefined privilege mode, a second exception is signalled, which requires a different privilege mode. The predefined privilege mode may have higher privileges than the different privilege mode. The processor may have a status register, which indicates the first exception has been signalled. The status register may be available from the debug interface. The first exception may be a debug exception, a memory fault or a memory translation fault. The predefined privilege level may be a hypervisor level and the different privilege level may be a guest operating system level. |
