Apparatuses, methods, and systems for jitter equalization and phase error detection

摘要

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

主权项

1. A circuit comprising:
a first transmission path to pass a first signal, the first transmission path including one or more circuit blocks to receive a supply voltage and to process the first signal; a second transmission path to pass a second signal, the second transmission path including one or more circuit blocks to receive the supply voltage and to process the second signal; a jitter equalizer coupled with the first transmission path to introduce a delay to the first signal to provide an alignment between the first and second signals, wherein an amount of the delay is based on a value of the supply voltage; an error detector to measure a phase error between the first and second signals; and a training controller to adjust a delay setting of the jitter equalizer based on the measured phase error to obtain a calibrated delay setting; and a supply modulator to modulate the supply voltage by a modulation frequency during a training process of the circuit.