发明名称 |
Techniques for interconnecting stacked dies using connection sites |
摘要 |
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites. |
申请公布号 |
US9287239(B2) |
申请公布日期 |
2016.03.15 |
申请号 |
US201113641680 |
申请日期 |
2011.04.13 |
申请人 |
Rambus Inc. |
发明人 |
Ware Frederick A.;Tsern Ely;Vogelsang Thomas |
分类号 |
H01L25/16;H01L23/538;H01L25/065;H01L25/18;H01L23/48 |
主分类号 |
H01L25/16 |
代理机构 |
Fenwick & West LLP |
代理人 |
Fenwick & West LLP |
主权项 |
1. An integrated circuit die, comprising:
conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof; a first core circuit located outside the contiguous region; and alignment circuitry configurable to couple a first subset of the connection sites to the first core circuit and to decouple a second subset of the connection sites from the first core circuit, the alignment circuitry additionally configurable to decouple the first subset of the connection sites from the first core circuit and to couple the second subset of the connection sites to the first core circuit. |
地址 |
Sunnyvale CA US |