SRAM with two-level voltage regulator

摘要

A programmable logic device (PLD) is provided with a two-level voltage regulator for powering SRAM cells within the device. In one example, a PLD includes a plurality of static random access memory (SRAM) cells configured to store a configuration for the programmable logic device. The PLD also includes a two-level voltage regulator configured to selectively charge a first power supply node to a reduced voltage and to an enhanced voltage that is greater than the reduced voltage. The SRAM cells are powered through a coupling to the first power supply node. The PLD also includes a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during a write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device.

主权项

1. A programmable logic device, comprising:
a plurality of static random access memory (SRAM) cells arranged into a plurality of rows;
a plurality of word lines corresponding to the plurality of rows, wherein each SRAM cell comprises a pair of access transistors having their gates coupled to the SRAM cell's row's word line;a plurality of word line drivers corresponding to the plurality of word lines, each word line driver being powered through a coupling to a second power supply node;a switch coupled between the first power supply node and the second power supply node, wherein the control circuit is configured to close the switch during a write operation so that a selected one of the word lines is charged to the reduced voltage and to open the switch during a read operation; a two-level voltage regulator configured to selectively charge a first power supply node to one of a reduced voltage and an enhanced voltage that is greater than the reduced voltage, wherein the SRAM cells are powered through a coupling to the first power supply node; a power regulator configured to charge the second power supply node to an operating voltage that is lower than the reduced voltage during the read operation so that a selected one of the word lines is charged to the operating voltage during the read operation; and a control circuit configured to control the two-level voltage regulator to charge the first power supply node to the reduced voltage during the write operation for the SRAM cells and to charge the first power supply node to the enhanced voltage during normal operation of the configured programmable logic device.