Dual-mode transistor devices and methods for operating same

摘要

A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

主权项

1. A device comprising:
a transistor including a semiconductor body including a channel region, a p-type source/drain terminal region adjacent a first side of the channel region and an n-type source/drain terminal region adjacent a second side of the channel region; a gate insulator on a surface of the semiconductor body over the channel region; a gate on the gate insulator over the channel region; a first assist gate on the gate insulator disposed on a first side of the gate overlying a portion of the channel region adjacent the p-type source/drain terminal region, and a second assist gate on the gate insulator disposed on a second side of the gate overlying a portion of the channel region adjacent the n-type source/drain terminal region; and an assist gate driver electrically connected to the first and second assist gates to apply bias voltages to the first and second assist gates, configured to switch the transistor between an n-channel mode in which the bias voltages are positive and a p-channel mode in which the bias voltages are negative.