发明名称 |
Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device |
摘要 |
MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.;The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET. |
申请公布号 |
US9287259(B2) |
申请公布日期 |
2016.03.15 |
申请号 |
US201214111549 |
申请日期 |
2012.04.09 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Shinohara Hirofumi;Nishida Yukio;Horita Katsuyuki;Yamashita Tomohiro;Oda Hidekazu |
分类号 |
H01L27/088;H01L29/66;H01L21/8238 |
主分类号 |
H01L27/088 |
代理机构 |
Shapiro, Gabor and Rosenberger, PLLC |
代理人 |
Shapiro, Gabor and Rosenberger, PLLC |
主权项 |
1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming an element isolation region in the surface of a first main surface of a semiconductor wafer to define an N channel active region and an adjacent P channel active region in the surface of the first main surface of the semiconductor substrate; (b) forming, over the first main surface of the semiconductor substrate, an N channel gate stack that traverses the N channel active region and constitutes an N channel MISFET; (c) forming, over the first main surface of the semiconductor substrate, a P channel gate stack that traverses the P channel active region and constitutes a P channel MISFET; and (d) prior to the steps (b) and (c) but after the step (a), forming an N channel threshold voltage adjusting element outward diffusion preventing region in the surface region of the element isolation region below and at the periphery of the N channel gate stack, wherein the N channel threshold voltage adjusting element outward diffusion preventing region is formed by implanting N channel threshold voltage adjusting element ions into the surface region of the element isolation region, wherein the N channel threshold voltage adjusting element outward diffusion preventing region is formed without forming the N channel threshold voltage adjusting element outward diffusion preventing region in the surface region of the element isolation region below and at the periphery of the P channel gate stack, wherein the N channel threshold voltage adjusting element is any of La, Y, Mg, or Sc, and wherein step (d) is performed without introducing the N channel threshold voltage adjusting element into the N channel active region. |
地址 |
Tokyo JP |