发明名称 |
Memory system and assembling method of memory system |
摘要 |
According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information. |
申请公布号 |
US9286960(B2) |
申请公布日期 |
2016.03.15 |
申请号 |
US201414445479 |
申请日期 |
2014.07.29 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Takeyama Yoshikazu;Nagai Yuji |
分类号 |
G11C8/00;G11C8/12;G11C16/20;H01L25/065;H01L23/31;H01L23/00;H01L25/18 |
主分类号 |
G11C8/00 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A memory system comprising:
a memory package including a plurality of memory chips, each of the memory chips including a non-volatile memory cell array; and a controller configured to select one memory chip from the memory package based on a chip enable and a chip address, wherein each of the memory chips includes a first storage unit configured to store therein first information that is n-bit information (n is an integer of 2 or more) compared to the chip address, the first information being used for identifying its own memory chip, a second storage unit configured to store therein second information for determining an effective bit of the n-bit first information, and a control unit configured to determine an effective bit of the n-bit first information and an effective bit of the chip address based on the second information. |
地址 |
Minato-ku JP |