Managing chip testing data

摘要

A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.

主权项

1. A system comprising:
a scan channel comprising a plurality of scannable latches, the scan channel configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip; an aperture configured to select at least one bit output during a scan out of the scan channel and further configured to mask other bits, the at least one bit corresponding to output from a subset of the plurality of scannable latches, the other bits corresponding to the plurality of scannable latches outside of the subset; and a storage configured to store the selected at least one bit unmodified and further configured to not store the masked other bits.