发明名称 論理回路エミュレータ及び論理回路エミュレータの制御方法
摘要 A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle.
申请公布号 JP5884729(B2) 申请公布日期 2016.03.15
申请号 JP20120512851 申请日期 2011.04.26
申请人 日本電気株式会社 发明人 鈴木 紀章
分类号 G06F11/22;G01R31/28;G06F17/50 主分类号 G06F11/22
代理机构 代理人
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