发明名称 |
Semiconductor device and method of fabricating same |
摘要 |
A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes. |
申请公布号 |
US9287397(B2) |
申请公布日期 |
2016.03.15 |
申请号 |
US201313947911 |
申请日期 |
2013.07.22 |
申请人 |
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION |
发明人 |
Cao GuoHao;Yang Guangli;Zhou Yang;Wang GangNing |
分类号 |
H01L29/66;H01L29/78;H01L21/768 |
主分类号 |
H01L29/66 |
代理机构 |
Innovation Counsel LLP |
代理人 |
Innovation Counsel LLP |
主权项 |
1. A method of fabricating a semiconductor device, comprising:
forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate; forming spacers on sidewalls of the gate electrodes; depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers; selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes, remains after the selective etch, and wherein a portion of the gate electrodes is exposed to form an exposed portion of the gate electrodes after the selective etch of the interconnection layer; forming a dielectric layer on the semiconductor substrate, the sidewalls of the spacers, and the exposed portion of the gate electrodes; and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes, wherein the electrical contact is selectively formed on a portion of the etched interconnection layer located between adjacent laterally opposite spacers. |
地址 |
CN |