Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array

摘要

Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.

主权项

1. A semiconductor integrated circuit device provided with a plurality of lead layers over a semiconductor substrate, comprising:
a plurality of first memory cells arranged along a first direction; a plurality of second memory cells arranged along the first direction; a first and a second bit lines each commonly connected to the plurality of first memory cells; a third and a fourth bit lines each commonly connected to the plurality of second memory cells; a plurality of word lines extending in a second direction, each of the plurality of word lines connected to one of the plurality of first memory cells and one of the plurality of second memory cells, respectively; a first, a second and a third P-well regions provided on a main surface of the semiconductor substrate; a first N-well region provided on the main surface of the semiconductor substrate and arranged between the first and second P-well regions; a second N-well region provided on the main surface of the semiconductor substrate and arranged between the second and third P-well regions; a first voltage supply lead comprised of a first lead layer of the plurality of the lead layers; a first supply path physically contacting a first portion of the first voltage supply lead opposite to the semiconductor substrate and supplying a first voltage to the first P-well region from the first voltage supply lead; a second supply path physically contacting a second portion of the first voltage supply lead, which is different from the first portion, opposite to the semiconductor substrate and supplying the first voltage to the second P-well region from the first voltage supply lead; a third supply path connecting to a third portion of the first voltage supply lead, which is different from the first and the second portions, opposite to the semiconductor substrate and supplying the first voltage to the third P-well region from the first voltage supply lead; a second voltage supply lead comprised of the first lead layer of the plurality of the lead layers; a fourth supply path physically contacting a fourth portion of the second voltage supply lead opposite to the semiconductor substrate and supplying a second voltage to the first N-well region from the second voltage supply lead; and a fifth supply path physically contacting a fifth portion of the second voltage supply lead, which is different from the fourth portion, opposite to the semiconductor substrate and supplying the second voltage to the second N-well region from the second voltage supply lead, wherein the first, the second, and the third portions are provided to be aligned linearly along the second direction in plan view, wherein the fourth and the fifth portions are provided to be aligned linearly along the second direction in plan view, wherein each of the plurality of first memory cells includes a first and a second P-channel transistors provided on the first N-well region, a first and a second N-channel transistors provided on the first P-well region, and a third and a fourth N-channel transistors provided on the second P-well; the first N-channel transistor and the first P-channel transistor configure a first inverter, the third N-channel transistor and the second P-channel transistor configure a second inverter with an input of the first inverter coupled to an output of the second inverter and with an output of the first inverter coupled to an input of the second inverter, the second N-channel transistor electrically connects the first bit line with the output of the first inverter, and the fourth N-channel transistor electrically connects the second bit line with the output of the second inverter with a gate of the fourth N-channel transistor coupled to a gate of the second N-channel transistor, and wherein each of the plurality of second memory cells includes a third and a fourth P-channel transistors provided on the second N-well region, a fifth and a sixth N-channel transistors provided on the second P-well region, and a seventh and an eighth N-channel transistors provided on the third P-well; the fifth N-channel transistor and the third P-channel transistor configure a third inverter, the seventh N-channel transistor and the fourth P-channel transistor configure a fourth inverter with an input of the third inverter coupled to an output of the fourth inverter and with an output of the third inverter coupled to an input of the fourth inverter, the sixth N-channel transistor electrically connects the third bit line with the output of the third inverter, and the eighth N-channel transistor electrically connects the fourth bit line with the output of the fourth inverter with a gate of the eighth N-channel transistor couple to a gate of the sixth transistor.