Apparatus and methods employing variable clock gating hysteresis for a communications port

摘要

An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.

主权项

1. An apparatus, comprising:
a communications port configured to communicate, in response to a clock signal, over a bus; and a clock signal generation circuit configured to generate the clock signal and to vary, in response to an address of a communications transaction of the communications port, a delay of the clock signal.