Reception circuit and semiconductor integrated circuit device

摘要

A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.

主权项

1. A reception circuit comprising:
a plurality of block circuits, each block circuit including: a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock; and an operation phase control circuit configured to include a phase detecting circuit that detects a phase of the second clock in each of the block circuits, and control the phase control circuit in each of the block circuits in such a way that the phases of the second clocks in the block circuits vary, wherein each of the block circuits comprises a clock data recovery circuit, each of the internal circuits comprises a demultiplexer, and the second clock comprises a frequency-divided clock obtained by frequency-dividing the phase-controlled first clock; and wherein each of the clock data recovery circuits comprises: a digital filter circuit configured to adjust a sampling timing between an input data signal and the frequency-divided clock; an operation control circuit configured to control an operation of the digital filter circuit in accordance with a control signal from the operation phase control circuit; and a frequency lock detector configured to detect whether a frequency of the frequency-divided clock has been locked by the digital filter circuit.