Silicon nitride (SiN) encapsulating layer for silicon nanocrystal memory storage

摘要

Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

主权项

1. A memory device made up of a plurality of memory cells on a semiconductor substrate, wherein a memory cell comprises a charge-trapping layer arranged between a control gate and a select gate, wherein the charge-trapping layer comprises:
a tunneling oxide layer formed between the control gate and the select gate along a surface of a select gate sidewall, the tunneling oxide extending upwardly to cover a top surface of the select gate; a control oxide layer formed between the control gate and the select gate along a surface of a control gate sidewall; a plurality of spherically-shaped silicon nanocrystals arranged between the tunneling oxide layer and the control oxide layer along a surface of the tunnel oxide layer; and an insulating encapsulating layer, which isolates the control oxide layer from the silicon nanocrystals and the tunnel oxide layer.