发明名称 Method, apparatus and system for responding to a row hammer event
摘要 Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.
申请公布号 US9286964(B2) 申请公布日期 2016.03.15
申请号 US201213725800 申请日期 2012.12.21
申请人 Intel Corporation 发明人 Halbert John B.;Bains Kuljit S.
分类号 G11C11/406;G11C11/4076 主分类号 G11C11/406
代理机构 Vincent Anderson Law PC 代理人 Vincent Anderson Law PC
主权项 1. A memory device comprising: a first bank including a first row and a second row physically adjacent to the first row; a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank; detect logic to configure the memory device in response to an indication that repeated access to the first row exceeds a threshold; row hammer response logic of the memory device, in response to the indication and prior to receipt of an expected targeted refresh command from an associated memory controller, to restrict access to the first bank for access other than a targeted refresh, to prepare for receipt of the targeted refresh command; and access logic to service a memory access command from the memory controller prior to receipt of the targeted refresh command, including the access logic to access the second bank in response to the memory access command, the access logic further to perform the targeted refresh of the second row in response to the targeted refresh command received by the memory device from the memory controller after the memory access command.
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