Forward error correction

摘要

Methods and circuits are disclosed for forward-error-correction (FEC) decoding. A plurality of symbols are received in an interleaved format of rows and columns of the symbols. A plurality of FEC decoding iterations are performed on the plurality of symbols. Each decoding iteration performs FEC decoding of the rows of the plurality of symbols and performs FEC decoding of the columns of the plurality of symbols. After performing the decoding iterations, rows in error and columns in error of the plurality of symbols are determined. In response to the determined rows in error and the determined columns in error matching a deadlock pattern, symbols at intersections of the determined rows and columns in error are determined. Bits of one or more symbols of the determined symbols are inverted. After the inverting of the bits, one or more of the FEC decoding iterations are performed.

主权项

1. A method for forward error correction (FEC) decoding, comprising:
receiving a plurality of symbols in an interleaved format of rows and columns of the symbols; performing a plurality of FEC decoding iterations on the plurality of symbols, each decoding iteration including:
performing FEC decoding of the rows of the plurality of symbols; andperforming FEC decoding of the columns of the plurality of symbols; after performing the FEC decoding iterations, determining rows in error of the plurality of symbols and columns in error of the plurality of symbols; and in response to the determined rows in error and the determined columns in error matching a deadlock pattern of a set of deadlock patterns:
determining symbols of the plurality of symbols at intersections of the determined rows in error and the determined columns in error; andinverting bits of one or more symbols of the determined symbols; and performing one or more of the FEC decoding iterations after the inverting of the bits.