| 发明名称 | Semiconductor device | ||
| 摘要 | A semiconductor device comprises a first semiconductor chip; and a second semiconductor chip provided on the first semiconductor chip with having chip-on-chip connection to the first semiconductor chip, wherein when seen from a direction perpendicular to an upper surface of the second semiconductor chip, an outline of the second semiconductor chip is larger than an outline of the first semiconductor chip, a plurality of electrode terminals for the first semiconductor chip are provided on an upper surface of the first semiconductor chip, the plurality of electrode terminals for the first semiconductor chip comprise one or more first covered terminals which are covered with the second semiconductor chip and one or more first uncovered terminals which are not covered with the second semiconductor chip. | ||
| 申请公布号 | US9287249(B2) | 申请公布日期 | 2016.03.15 |
| 申请号 | US201314389621 | 申请日期 | 2013.03.12 |
| 申请人 | PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. | 发明人 | Kinoshita Tomohiro;Takahashi Eiji;Komatsu Naoki;Uriu Kazuhide |
| 分类号 | H01L25/18;H01L25/065;H01L23/498;H01L23/538;H01L23/00;H04N21/426;H04N5/775 | 主分类号 | H01L25/18 |
| 代理机构 | Hamre, Schumann, Mueller & Larson, P.C. | 代理人 | Hamre, Schumann, Mueller & Larson, P.C. |
| 主权项 | 1. A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip provided on the first semiconductor chip with having chip-on-chip connection to the first semiconductor chip; and a first extension part which is formed on a periphery of or lateral to the first semiconductor chip and supports the second semiconductor chip, wherein when seen from a direction perpendicular to an upper surface of the second semiconductor chip, an outline of the second semiconductor chip is larger than an outline of the first semiconductor chip, a plurality of electrode terminals for the first semiconductor chip are provided on an upper surface of the first semiconductor chip, the plurality of electrode terminals for the first semiconductor chip comprise one or more first covered terminals which are covered with the second semiconductor chip and one or more first uncovered terminals which are not covered with the second semiconductor chip, and wherein one or more extension terminals are provided on an upper surface of the first extension part, and at least one of the extension terminals and at least one of the first covered terminals are connected by rewiring. | ||
| 地址 | Osaka JP | ||